1. Field of the Invention
The invention relates to a method for fabricating a transistor in a semiconductor device, and more particularly, to a method for fabricating a transistor including a recess gate.
2. Brief Description of Related Technologies
As the degree of integration of memory devices, such as a Dynamic Random Access Memory (DRAM), is increased, a design rule of the device has been decreased. The decrease of the design rule results in a decrease of a Critical Dimension (CD) of a gate of a transistor and, thus, a shortening of the length of a channel between a source and a drain. The shortening of the channel length results in a short channel effect, which can result in deterioration of the operation properties of the transistor, such as, for example, an increase in leakage current and a reduction in refresh properties.
A punch-through between a source region and a drain region of the transistor due to the short channel effect can act as a main cause of malfunction of the transistor device. Also, a shortened channel length of the transistor and variation in the threshold voltage of the channel can have a relatively large influence on the operation properties of the transistor. As the channel length is shortened, it becomes more difficult to gradually control the threshold voltage in the channel, i.e. a threshold voltage control margin is sharply weakened. The variation in the threshold voltage can inhibit operational stability of the semiconductor device.
In order to compensate for the short channel effect caused by the reduction of the channel length, attempts have been made to produce more channel length within limited area on a semiconductor substrate. For example, a recess gate structure can be formed by etching an active region of the semiconductor substrate under a gate to form a recess groove, and the gate can then be formed so as to fill the recess groove. The recess groove is generally formed by selectively etching the surface of the active region.
When forming a plurality of gates at the same time, the etch depth by the selective etch process is varied from position to position, which can result in the recess grooves having different depths. Non-uniformity of the depths of the recess grooves causes the channel length to be varied. Therefore, since the channel length is varied among the memory cell transistors, the threshold voltage of the transistor is also varied. It is difficult to maintain reliably uniform operation properties of the memory cell transistors when the distribution in the threshold voltage of the cell transistors is varied.
Therefore, a method for forming a transistor capable of improving the uniformity of CD of the channel length, while ensuring increased channel length with respect to the limited gate CD is needed.